Latches and Flip-Flops 1 - The SR Latch

latches and flip-flops are the building

blocks of computer memory in this

particular video we'll focus on the

so-called Sr latch later we'll see how

this circuit can be

enhanced the set reset latch or Sr latch

for short can be thought of as a one bit

memory it can be put into one of two

stable output States triggered by an

input

pulse the circuit remembers the this

state until it's changed Again by

another input pulse or until the power's

removed for this reason the circuit is

known as a bable

latch before we consider the

construction of Sr latches let's remind

ourselves of some fundamental logic

gates this is an or gate and this is the

truth table that describes Its Behavior

any combination of inputs A and B

results in a one at output p except when

both inputs are zero in which case the

output is

zero this is an and gate and this is the

truth table that describes Its Behavior

any combination of inputs A and B

results in a zero at output P except

when both inputs are one in which case

the output is

one if we modify the output of a regular

or gate by inverting it with a not gate

then we can swap the zero for a one and

the ones for zeros in the output column

of the truth

table in a similar fashion we can invert

the output of a regular and gate then we

can swap the zeros for ones and the one

for a zero in the output column of this

tooth

table each of these gate combinations

has its own name and its own symbol they

are are known as the Norgate and the

nand

gate the Norgate only produces an output

of one if both of the inputs are zero

the nand gate only produces an output of

zero if both of the inputs are

one the SR latch can be built using one

of these two basic building

blocks let's start by considering an Sr

latch built from nor

gates in this Norgate version of an Sr

latch two nor gates are connected

together in such a way as the output of

each nor gate is one of the inputs of

the other this crosscoupling of two

gates results in a form of positive

feedback Sr latches like all electronic

circuits require power to work the power

connections aren't shown on this

diagram the SR lat has two inputs R and

S and the output Q the SR latch also

makes the inverse of the output

available on this diagram you can see

not q a q with a bar above

it the starting State here is that S and

R are both low that is both inputs are

zero Q is high that is the output is one

and not Q the inverse of this is

zero both of the inputs of the top n

gate are zero so the output of the top

gate is one this is exactly what you

would expect from a

Norgate the inputs of the lower Norgate

are one and zero so the output of the

Lower Gate is

zero because Q is one the latch is

currently storing

one now we apply a pulse to input R to

reset the

latch this changes the the output of the

top gate and then this is fed back into

the Lower Gate the lower Gate's output

also changes and this is fed back into

the top gate the pulse that was applied

to reset the SR latch is then removed

and R is zero

again but the output at Q is now zero so

the latch is now storing a

zero in order to store a one again a

pulse must be applied to input s which

will set the lat

again notice how the various changes are

propagated around the

circuit the set pulse is then

removed and the circuit is now latched

into a set State it's storing a one

again notice that if another set pulse

is applied it has no

effect applying a set pulse at s will

always for Force the latch into a set

State regardless of the previous state

of the latch similarly applying a reset

pulse will always Force the latch into a

reset state it should be noted that S

and R are never left high that is

neither is ever set continuously to the

value one the latch is controlled by

pulses

only this gives us an unusual looking

truth table

when both S and R are set to zero Q may

be one or it may be zero depending on

the previous state of the circuit let's

examine the truth table as this Sr latch

is reset

again the reset pulse is applied s is

zero R is one output Q is zero and its

inverse not Q is one the SR latch is

storing a

zero the reset pulse is removed both S

and R are zero again output Q remains at

zero and its inverse remains at one the

SR latch is still storing a

zero a set pulse is applied s is one and

R is zero the output Q becomes one and

its inverse becomes

zero the set pulse is removed s is zero

and R is zero output Q is still one and

not Q is of course

zero now the only circumstance we

haven't considered is when both inputs S

and R are set to one at the same

time if this were to occur we'd be

telling the SR latch to set the value of

Q to both one and zero

simultaneously in reality Q would become

zero and not Q would also become zero

this would sort itself out if one of the

inputs fell to zero before the other for

example if r fell to zero first with s

still at one then Q would become one

again if however both inputs were at one

and both fell to zero at the same time

we'd have what's known as a race

condition between the two gates they'd

be racing each other to feed back their

new output and it's impossible to know

which one would win hence if both puts

are high the next state of the latch

can't be determined this is not a state

that the latch should ever be in it's

illegal it's

invalid most of the time inputs S and R

should both be at zero and only

momentarily will one or the other input

become one and at any time while it's

operating the SR latch should either be

in a set state or a reset state with q

and not Q the opposite of each other

one final piece of terminology this type

of Sr latch is said to be an active High

Sr latch because the normal condition

for S andr is low and a high pulse at

one of these inputs is required to bring

about a

change now let's consider an Sr latch

built from nand Gates here's a reminder

of the nandate truth table only when

both inputs are high is the output

low the wiring of this SL latch is the

same but notice that input s is at the

top now and R is at the

bottom here's a truth table for this

variation of the SR latch it's a little

different from the truth table we've

just seen because this latch behaves

differently the difference is that R and

S are kept High most of the time here we

can see that output Q is zero so the

latch is storing a zero when input s is

made low momentarily that is when s

becomes zero and R is still one the

output at Q becomes one the latch is now

storing a one and S can be returned to

its normal high

State when R is set low momentarily the

output at Q is changed to

zero R can then return to its normal

high value and the latch is now storing

a zero

again an Sr latch built from nand Gates

like this is more explicitly known as an

active low Sr

latch an Sr latch based on nand Gates

also has a forbidden state that is when

both S and R are simultaneously

zero this would result in an illegal

state in which both q and its complement